| Department | Computer Engineering |
| Knowledgment area | Computer Architecture and Technology |
| Research | Research group Grupo de Arquitectura de Ordenadores |
| Research lines | Reconfigurable hardware, data compression, digital arithmetic, image and video encoding |
| Contacto | UDC directory |
| Orcid id0000-0001-8768-2240 ResearcherIDF-7633-2016 Scopus7005282712 | |
This section shows the teaching given in degrees, masters and other officers studies in last 6 years.
| Subject and involved studies | Type | Distance hours | Total hours |
|---|---|---|---|
|
Final Year Dissertation. Mention in Information Systems
Degree in Computer Engineering
|
Compulsory | 0 | 0.5 |
|
Final Year Dissertation. Mention in Information Technology
Degree in Computer Engineering
|
Compulsory | 0 | 2 |
|
Final Year Dissertation. Mention in Software Engineering
Degree in Computer Engineering
|
Compulsory | 0 | 1.5 |
|
Master's Dissertation
Master in High Performance Computing
|
Compulsory | 0 | 2 |
| Subject and involved studies | Type | Distance hours | Total hours |
|---|---|---|---|
| Fundamentals of Computers | Core | 0 | 65 |
| Hardware/Software Co-Design | Optional | 0 | 42 |
| High Performance Infrastructures | Compulsory | 12 | 33 |
| Master's Dissertation | Compulsory | 0 | 3.33333333333333 |
| Subject and involved studies | Type | Distance hours | Total hours |
|---|---|---|---|
|
Fundamentals of Computers
Degree in Computer Engineering
|
Core | 0 | 55 |
|
Hardware/Software Co-Design
Degree in Computer Engineering
|
Optional | 0 | 42 |
|
High Performance Infrastructures
Master in High Performance Computing
|
Compulsory | 12 | 33 |
| Subject and involved studies | Type | Distance hours | Total hours |
|---|---|---|---|
|
Fundamentals of Computers
Degree in Computer Engineering
|
Core | 0 | 45 |
|
Hardware/Software Co-Design
Degree in Computer Engineering
|
Optional | 0 | 42 |
|
High Performance Infrastructures
Master in High Performance Computing
|
Compulsory | 12 | 33 |
| Subject and involved studies | Type | Distance hours | Total hours |
|---|---|---|---|
|
Fundamentals of Computers
Degree in Computer Engineering
|
Core | 0 | 65 |
|
Hardware/Software Co-Design
Degree in Computer Engineering
|
Optional | 0 | 42 |
|
High Performance Infrastructures
Master in High Performance Computing
|
Compulsory | 12 | 33 |
| Subject and involved studies | Type | Distance hours | Total hours |
|---|---|---|---|
|
Fundamentals of Computers
Degree in Computer Engineering
|
Core | 0 | 69 |
|
Hardware/Software Co-Design
Degree in Computer Engineering
|
Optional | 0 | 42 |
|
High Performance Infrastructures
Master in High Performance Computing
|
Compulsory | 0 | 21 |
Defined tutoring by teacher for 2023/2024 academic course.
| Quarter | Day | Site |
|---|---|---|
| 1st quarter |
Thursday
11:30 a 13:30 |
Despacho 1.07 |
| 1st quarter |
Friday
11:30 a 13:30 |
Despacho 1.07 |
| 2nd quarter |
Tuesday
09:30 a 11:30 |
Teams |
| 2nd quarter |
Thursday
11:30 a 13:30 |
Teams |
Directed or codirected by current teacher since 2013 year.
| Analysis of the feasibility of implementing a network storage based on ATA over Ethernet for checkpointing |
Select merit type and year to query research merits.
Arquitecturas, Frameworks y Aplicaciones de la Computación de Altas Prestaciones
| Funding entity | Ministerio de Ciencia e Innovación |
| Main researches | TOURIÑO DOMÍNGUEZ JUAN (IP1) / RODRIGUEZ ÁLVAREZ GABRIEL (IP2) |
| Type | Proyecto Programas Nacionales |
| Dates | From 01/09/2023 to 31/08/2026 |
AXUDAS PARA A CONSOLIDACIÓN E ESTRUTURACIÓN DE UNIDADES DE INVESTIGACIÓN COMPETITIVAS.GRC 2021
| Funding entity | Consellería de Cultura, Educación e Ordenación Universitaria |
| Main researches | Juan Touriño Domínguez |
| Type | Proyecto Programas Autonomicos |
| Dates | From 01/01/2021 to 20/11/2024 |
Desafíos Actuales en HPC: Arquitecturas, Software y Aplicaciones
| Funding entity | Ministerio de Ciencia e Innovación |
| Main researches | Touriño Dominguez, Juan e Doallo Biempica, Ramón |
| Type | Proyecto Programas Nacionales |
| Dates | From 01/06/2020 to 31/05/2023 |
NUEVOS DESAFIOS EN COMPUTACION DE ALTAS PRESTACIONES: DESDE ARQUITECTURAS HASTA APLICACIONES (II)
| Funding entity | Ministerio de Economía y Competitividad (MINECO) |
| Main researches | Ramón Doallo Biempica, Juan Touriño Domínguez |
| Type | Proyecto Programas Nacionales |
| Dates | From 30/12/2016 to 29/12/2019 |
FPGA Acceleration of Optimization Problems using Differential Evolution (Intel Hardware Accelerator Research Program)
| Funding entity | Intel Corporation |
| Main researches | Roberto Rodríguez Osorio |
| Type | Proyecto Internacional |
| Dates | From 23/11/2016 to 31/12/2017 |
Nuevos Desafíos en Computación de Altas Prestaciones: desde Arquitecturas hasta Aplicaciones
| Funding entity | Ministerio de Economía y Competitividad |
| Main researches | Ramón Doallo Biempica y Juan Touriño Domínguez |
| Type | Proyecto Programas Nacionales |
| Dates | From 01/01/2014 to 31/12/2017 |
Consolidación y Estructuración de Unidades de Investigación Competitivas: Grupo de Arquitectura de Computadores de la Universidad de A Coruña (Grupo de Referencia Competitiva)
| Funding entity | Xunta de Galicia |
| Main researches | Ramón Doallo Biempica |
| Type | Proyecto Programas Autonomicos |
| Dates | From 01/01/2013 to 31/12/2016 |
High-Performance Embedded Architectures and Compilation Network of Excellence, HiPEAC-3 NoE
| Funding entity | Union Europea |
| Main researches | Koen De Bosschere |
| Type | Proyecto UE |
| Dates | From 01/02/2012 to 31/01/2016 |
Hardware y Software para Computación de Altas Prestaciones
| Funding entity | Ministerio de Economía y Competitividad |
| Main researches | Javier Díaz Bruguera (USC) |
| Type | Proyecto Programas Nacionales |
| Dates | From 01/01/2011 to 12/07/2015 |
Red Gallega de Computación de Altas Prestaciones II
| Funding entity | Xunta de Galicia |
| Main researches | Ramón Doallo Biempica |
| Type | Proyecto Programas Autonomicos |
| Dates | From 01/01/2010 to 31/12/2011 |
Consolidación y Estructuración de Unidades de Investigación Competitivas: Grupo de Arquitectura de Computadores de la Universidad de A Coruña (Grupo de Referencia Competitiva)
| Funding entity | Xunta de Galicia |
| Main researches | Ramón Doallo Biempica |
| Type | Proyecto Programas Autonomicos |
| Dates | From 01/01/2010 to 31/12/2012 |
Soporte para Aplicaciones de Paso de Mensajes en Supercomputadores: Tolerancia a Fallos y Maleabilidad
| Funding entity | Consellería de Educación e Ordenación Universitaria |
| Main researches | María José Martín Santamaría |
| Type | Proyecto Programas Autonomicos |
| Dates | From 01/11/2010 to 31/10/2013 |
Floating Point Calculation of the Cube Function on FPGAs
| Authors | Roberto Rodriguez Osorio |
| Journal | IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS Vol. 34 Num. 1 (pages 372 to 382) |
| DOI | https://doi.org/10.1109/tpds.2022.3220039 |
Implementation of a Motion Estimation Algorithm for Intel FPGAs using OpenCL
| Authors | ManuelDeCastroCaballero, Roberto Rodriguez Osorio, David López Vilariño, Arturo González-Escribano, Diego_R_Llanos |
| Journal | JOURNAL OF SUPERCOMPUTING |
| DOI | https://doi.org/10.1007/s11227-023-05051-3 |
An efficient ant colony optimization framework for HPC environments
| Authors | Patricia González, Roberto Rodriguez Osorio, Xoán C. Pardo, Julio R. Banga, Ramón Doallo |
| Journal | Applied Soft Computing Vol. 114 |
| DOI | https://doi.org/10.1016/j.asoc.2021.108058 |
Comparison of Hardwired and Microprogrammed Statechart Implementations
| Authors | Javier Cereijo García, Roberto Rodriguez Osorio |
| Journal | Electronics Vol. 9 Num. 7 |
Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors
| Authors | Roberto Rodriguez Osorio, Gabriel Rodríguez Álvarez |
| Journal | IEEE Access Vol. 7 (pages 56353 to 56366) |
| DOI | https://doi.org/10.1109/access.2019.2913743 |
A Fast Algorithm for Constructing Nearly-Optimal Prefix Codes
| Authors | Roberto Rodriguez Osorio, Patricia González |
| Journal | SOFTWARE-PRACTICE & EXPERIENCE Vol. 46 Num. 10 (pages 1299 to 1316) |
| DOI | https://doi.org/10.1002/spe.2375 |
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard
| Authors | Roberto R. Osorio, Javier D. Bruguera |
| Journal | Journal of Signal Processing Systems Vol. 72 Num. 2 (pages 119 to 132) |
Improving Scalability of Application-Level Checkpoint-Recovery by Reducing Checkpoint Sizes
| Authors | Cores Gonzalez, Ivan, Gabriel Rodríguez Álvarez, María J. Martín, Patricia González, Roberto Rodriguez Osorio |
| Journal | NEW GENERATION COMPUTING Vol. 31 Num. 3 (pages 163 to 185) |
Performance analysis of massively parallel embedded hardware architectures for retinal image processing
| Authors | Alejandro Nieto, Victor Brea, David L. Vilarino, Roberto Rodriguez Osorio |
| Journal | EURASIP JOURNAL ON IMAGE AND VIDEO PROCESSING (pages 0 to 0) |
High-Throughput Architecture for H.264/AVC CABAC Compression System
| Authors | Roberto R. Osorio, Javier D. Bruguera |
| Journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY Vol. 16 Num. 11 (pages 1376 to 1384) |
View-dependent, scalable Texture Streaming in 3D QoS with MPEG-4 Visual Texture Coding
| Authors | Gauthier Lafruit, Eric Delfosse, Roberto Rodriguez Osorio, Wolfgang van Raemdonck, Vissarion Ferentinos, Jan Bormans |
| Journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY Vol. 14 Num. 7 (pages 1021 to 1031) |
High speed 4-symbol arithmetic encoder architecture for embedded zero tree-based compresion
| Authors | Roberto Rodriguez Osorio, Vanhoof, Bart |
| Journal | JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY Vol. 33 Num. 3 (pages 267 to 276) |
Timing architecture for ESS
| Autor | Javier Cereijo García |
| Director/s | Daniel Piso Fernández; Roberto Rodríguez Osorio |
| Scope | Facultad de Informática |
| Qualification | Sobresaliente Cum Laude |
A Microprogrammed Approach for Implementing Statecharts
Euromicro Conference on Digital System Design, 2019
International
| Authors | JavierCereijoGarcia, Roberto Rodriguez Osorio |
| Organization | IEEE Computer Society |
| Place | Kallithea (Grecia) |
| DOI | https://doi.org/10.1109/dsd.2019.00015 |
Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities
XXXIV Conference on Design of Circuits and Integrated Systems, DCIS 2019
International
| Authors | JavierCereijoGarcia, University of A Coruna |
| Place | Bilbao (España) |
Timing System at ESS
8th Int. Particle Accelerator Conf. (IPAC'17)
International
| Authors | Javier Cereijo García, Timo Korhonen, J.H. Lee, Roberto Rodriguez Osorio, Daniel Piso Fernández |
| Place | Copenhagen (Dinamarca) |
| DOI | https://doi.org/10.18429/jacow-ipac2017-thpva064 |
Transaction Level and RTL Modeling of an Architecture for Network Data Compression within Ethernet Switches in Large File Transfer Scenarios
Design of Circuits and Integrated Systems (DCIS 2016)
International
| Authors | Roberto Rodriguez Osorio |
| Place | Granada (España) |
| DOI | https://doi.org/10.1109/dcis.2016.7845360 |
Modular Architecture for Multiple Transforms in Modern Video Standards
Design of Circuits and Integrated Systems (DCIS 2016)
International
| Authors | Roberto Rodriguez Osorio |
| Place | Granada (España) |
| DOI | https://doi.org/10.1109/dcis.2016.7845377 |
Pipelined FPGA Implementation of Numerical Integration of the Hodgkin-Huxley Model
2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
International
| Authors | Roberto Rodriguez Osorio |
| Place | Londres (Reino Unido) |
| DOI | https://doi.org/10.1109/asap.2016.7760794 |
Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage Networks
Euromicro Symposium on Digital System Desing Architecture, Methods and Tools, DSD, 2013
International
| Authors | Ángela Souto Vieites, Roberto Rodriguez Osorio |
| Organization | IEEE Computer Society |
| Place | Santander (España) |
Fast Construction of Nearly-Optimal Prefix Codes without Probability Sorting
Data Compression Conference 2012
International
| Authors | Patricia González, Roberto Rodriguez Osorio |
| Organization | Brandeis University |
| Place | Snowbird (Estados Unidos) |
Aprender Arquitectura de Computadores con la Herramienta Simula3MS
XVI Jornadas de Enseñanza Universitaria de la Informática (JENUI)
National
| Authors | Margarita Amor López, Raquel Concheiro Figueroa, Patricia González, Montserrat Bóo Cepeda, Juan Ángel Lorenzo Del Castillo, Daniel Piso Fernández, Roberto Rodriguez Osorio |
| Place | Santiago de Compostela (España) |
An FPGA Architecture for CABAC Decoding in Manycore Systems
19th International Conference on Application Specific Systems, Architectures and Processors. ASAP 2008
International
| Authors | Roberto Rodriguez Osorio, Javier Díaz Bruguera |
| Organization | IEEE Computer Society |
| Place | Leuven (Bélgica) |
A unified architecture for H.264 multiple block-size DCT and fast and low cost quantization
EUROMICRO Symposium on Digital Systems Design. DSD 2006.
International
| Authors | Roberto Rodriguez Osorio, Javier Díaz Bruguera |
| Organization | IEEE Computer Society |
| Place | Dubrovnik (Croacia) |
A combined memory compression and hierarchical motion estimation architecture for video encoding in embedded systems
EUROMICRO Symposium on Digital Systems Design. DSD 2006.
International
| Authors | Roberto Rodriguez Osorio, Javier Díaz Bruguera |
| Organization | IEEE Computer Society |
| Place | Dubrovnik (Croacia) |
A new architecture for fast arithmetic coding in H.264 advanced video coder
Euromicro Symposium on Digital System Desing Architecture, Methods and Tools, DSD, 2005
International
| Authors | Roberto Rodriguez Osorio, Javier Díaz Bruguera |
| Organization | IEEE Computer Society |
| Place | Oporto (Portugal) |
Arithmetic Coding Architecture for H.264/AVC CABAC Compression System
EUROMICRO Symposium on Digital Systems Design, DSD 2004
International
| Authors | Roberto Rodriguez Osorio, Javier Díaz Bruguera |
| Organization | IEEE Computer Society |
| Place | Rennes (Francia) |
Academic or management positions held by teacher.